// man resume

$ cat resume.txt

resume.txt

❯ echo $NAME

Daniel Artis

Electrical & Software Engineer

Los Angeles, CA · [dkartis1@gmail.com](mailto:dkartis1@gmail.com) ·

github.com/dartis · linkedin.com/in/dkartis

// experience

Staff Software Engineer 2024 — present
Northrop Grumman
  • Chief Product Owner/SEIT Lead of a research SW productization program using C++
  • Leading modularization and rearchitecture effort to productize SW
  • Developed flexible architecture for feature selection
Principal Software Engineer 2021 — 2024
Raytheon
  • Developed C++ simulation code for satellite systems using Windows and Linux
  • Developed validation library and test code for flight and sim SW
  • Developed C++ and Python tools to support development
  • Automated manual tasks with batch and bash scripts
Senior Software Engineer 2020 — 2021
WhiteFox
  • Developed C++ API for AD9361 Tx and FPGA module configuration.
  • Developed features, fixed network delays, and added status messaging to a Linux based C++ drone detection system
  • Developed features for Linux based Python drone detection system and resolved legacy client disconnection issues
  • Developed ARM to FPGA interface for FPGA module configuration. Developed a configurable sweeping tone generator and reduced multiple images into a single configurable image
Senior Software Engineer II 2018 — 2020
Raytheon
  • Developed radar software on Green Hills Integrity using C and ADA.
  • Developed Python tools to implement a custom address space layout randomization (ASLR) technique for ELF files, setup and compile projects, and extract and format binary data.
Lead Engineer 2012 — 2018
Booz Allen Hamilton/ARINC
  • Developed Java app to interface with Ettus SDR and create a LTE network. Developed app with Linux console interface for LTE eNodeB
  • Developed C# scheduling app using DevExpress. Selected and implemented encryption and authentication for custom protocol
  • Developed C++ host code interfaces to FPGA based GPS receiver, eLoran receiver, and custom modem
  • Implemented CODEC (demultiplexer, descrambler, deinterleaver, variable rate viterbi decoder) in VHDL and modeled in Python for FPGA based receiver
  • Developed system design, FPGA infrastructure, and digital front end for FPGA in VHDL for custom eLoran receiver FPGA PCB with interface to ADC, clock generator, and gain control in VHDL and the API in C
  • Customized Ettus USRP’s Verilog FPGA design and C++ driver to work with custom SDR board
  • Implemented VHDL code for FPGA based GPS simulator
  • Developed Android app with GNU Radio interface and C++ blocks that ran through the JNI
Electrical Engineer I 2011 — 2012
Raytheon
  • Implemented test benches in Verilog and SystemVerilog using the Open Verification Method (OVM)
  • Tested and fixed redesigned waveform generating RF module in preparation to go into production
  • Tested and troubleshot production RF modules and units ensuring on or ahead of schedule sell off
Tech Student Senior (Intern) Jun 2010 — Sep 2010
Raytheon
  • Ran ASIC simulations to verify design constraints were met
  • Created and edited implementation and design requirement documents
  • Verified test benches while testing all design constraints
  • Verified hardware issue through ModelSim simulations

// education

M.S. Computer Science 2020 — 2024
Georgia Institute of Technology
  • Specialization: Machine Learning
  • Relevant Coursework: Machine Learning, Deep Learning, Natural Language Processing
B.S. Electrical Engineering 2007 — 2011
Cal Poly University, San Luis Obispo
  • Senior project: Digital Modulations Using the Universal Software Radio Peripheral
  • Concentration: Communications
  • Clubs: Robotics Club, IEEE

// skills

Languages
C/C++ Python Java C# Kotlin VHDL Verilog SystemVerilog ADA Javascript TypeScript Bash Batch
Tools
Visual Studio VSCode Android Studio Vivado Xilinx ISE Xilinx SDK Eclipse MATLAB ModelSim Git GitLab GitHub Docker SVN Jira Confluence CMake Make Gradle GDB Valgrind
Hardware
FPGA Oscilloscope Spectrum Analyzer Logic Analyzer Software Defined Radio (SDR) Soldering
OS
Linux Windows macOS Green Hills Integrity VxWorks
Protocols
SPI I2C UART UDP TCP

// certifications & awards

certs.log

❯ ls awards/

Bravo Award: 7/2025

RStar: 12/2011, 9/2019, 6/2023

Technical Honors: 3/2020

High Five: 8/2013, 2/2017

Living Our Values: 10/2017, 3/2018